EVAL-AD7321CB【PDF 31/36 页】500 kSPS, 2-Channel, Software-Selectable

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AD7321

SERIAL INTERFACE

Figure 50 shows the timing diagram for the serial interface of

the AD7321. The serial clock applied to the SCLK pin provides

the conversion clock and controls the transfer of information to

and from the AD7321 during a conversion.

Rev. 0 | Page 31 of 36

Data is clocked into the AD7321 on the SCLK falling edge. The

three MSBs on the DIN line are decoded to select which register

is being addressed. The control register is a 12-bit register. If the

control register is addressed by the three MSBs, the data on the

DIN line is loaded into the control on the 15

SCLK falling

edge. If the range register is addressed, the data on the DIN line is

loaded into the addressed register on the 11

SCLK falling edge.

The

process. The falling edge of CS puts the track-and-hold into

hold mode and takes the bus out of three-state. Then the analog

input signal is sampled. Once the conversion is initiated, it

requires 16 SCLK cycles to complete.

signal initiates the data transfer and the conversion

Conversion data is clocked out of the AD7321 on each SCLK

falling edge. Data on the DOUT line consists of two leading

ZEROs, a channel identifier bit, a sign bit, and a 12-bit conversion

result. The channel identifier bit is used to indicate which channel

corresponds to the conversion result. The first ZERO bit is clocked

out on the

CS falling edge, and the second bit is clocked out on

the first SCLK falling edge.

The track-and-hold goes back into track mode on the 14

SCLK

rising edge. On the 16

SCLK falling edge, the DOUT line returns

to three-state. If the rising edge of CS occurs before 16 SCLK cycles

have elapsed, the conversion is terminated, and the DOUT line

returns to three-state. Depending on where the

high, the addressed register may be updated.

CS signal is brought

ZERO

WRITE

ZERO

REG

SEL

LSB

CARE

MSB

ADD0

SIGN

DB11

DB10

DB2

DB1

DB0

QUIET

CONVERT

SCLK

DOUT

THREE-

STATE

THREE-STATE

DIN

ZERO

IDENTIFICATION BIT

Figure 50. Serial Interface Timing Diagram (Control Register Write)

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